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| SG6932 -- PFC / Forward PWM Controller May 2008 SG6932 PFC / Forward PWM Controller Features Interleaved PFC/PWM Switching Low Operating Current Innovative Switching-Charge Multiplier-divider Multi-vector Control for Improved PFC Output Transient Response Average Current Mode for Input-current Shaping PFC Over-voltage and Under-voltage Protections PFC and PWM Feedback Open-loop Protection Cycle-by-cycle Current Limiting for PFC/PWM Slope Compensation for PWM Selectable PWM Maximum Duty Cycle: 50%, 65% Brownout Protection Power-on Sequence Control and Soft-start Description The highly integrated SG6932 is designed for power supplies with boost PFC and forward PWM. It requires very few external components to achieve versatile protections and compensation. It is available in 16-pin DIP and SOP packages. The proprietary interleave-switching feature synchronizes the PFC and PWM stages and reduces switching noise. At light load, the switching frequency is continuously decreased to reduce power consumption. For PFC stage, the proprietary multi-vector control scheme provides a fast transient response in a lowbandwidth PFC loop; in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, SG6932 shuts off to prevent extra-high voltage on output. For the forward PWM stage, the synchronized slope compensation ensures the stability of the current loop under continuous-conduction-mode (CCM) operation. Hiccup operation during output overloading is guaranteed. The soft-start and programmable maximum duty cycle ensure safe operation. SG6932 provides complete protection functions, such as brownout protection and RI open/short latch off. Applications Switch-mode Power Supplies with Active PFC Servo-system Power Supplies PC-ATX Power Supplies Ordering Information Part Number SG6932DZ SG6932SZ Operating Temperature Range -40C to +85C -40C to +85C Package 16-pin Dual In-Line Package (DIP) 16-pin Small Outline Package (SOP) Eco Status RoHS RoHS Packing Method Tube Tape & Reel For Fairchild's definition of "green" Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com SG6932 -- PFC / Forward PWM Controller Application Diagram Figure 1. Typical Application (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 2 SG6932 -- PFC / Forward PWM Controller Block Diagram Figure 2. Function Block Diagram (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 3 SG6932 -- PFC / Forward PWM Controller Marking Information SG6932TP XXXXXXXXYWWV T: D=DIP, S=SOP P : Z =Lead Free + ROHS Compatible XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location Figure 3. Top Mark Pin Configuration VRMS RI IEA IPFC IMP ISENSE FBPWM IPWM 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 IAC VEA FBPFC SS VDD OPFC GND OPWM Figure 4. Pin Configuration (Top View) (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 4 SG6932 -- PFC / Forward PWM Controller Pin Definitions Pin # 1 Name VRMS Description Line-Voltage Detection. The pin is used for PFC multiplier and brownout protection. Oscillator Setting. One resistor connected between RI and ground determines the switching frequency. A resistor with resistance between 12 ~ 47k is recommended. The switching frequency is equal to [1560 / RI]kHz, where RI is in k. For example, if RI is 24k, the switching frequency is 65kHz. Output of PFC Current Amplifier. The signal from this pin is compared with an internal sawtooth to determine the pulsewidth for PFC gate drive. Inverting Input of PFC Current Amplifier. Proper external compensation circuits result in excellent input power factor via average-current-mode control. Non-inverting Input of PFC Current Amplifier and Output of Multiplier. Proper external compensation circuits result in excellent input power factor via average-current-mode control. Peak Current Limit Setting for PFC. PWM Feedback Input. The control input for voltage-loop feedback of PWM stage. It is internally pulled HIGH through a 6.5k resistor. An external opto-coupler from the secondary feedback circuit is usually connected to this pin. PWM Current Sense. The current sense input for the PWM stage. Via a current sense resistor, this pin provides the control input for peak-current-mode control and cycle-by-cycle current limiting. PWM Gate Drive. The totem-pole output drive for PWM MOSFET. clamped under 18V to protect the MOSFET. Ground. The power ground. PFC Gate Drive. The totem-pole output drive for the PFC MOSFET. This pin is internally clamped under 18V to protect the MOSFET. Supply. The power supply pin. The threshold voltages for start-up and turn-off are 14V and 10V, respectively. The operating current is lower than 10mA. PWM Soft-Start. During startup, the SS pin charges an external capacitor with a 50A constant current source. The voltage on FBPWM is clamped by SS during startup. In the event of a protection condition occurring and/or PWM being disabled, the SS pin is quickly discharged. The voltage of SS pin can be used to select 50% or 65% maximum duty cycle. Voltage Feedback Input for PFC. The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin is connected to the PFC output through a divider network. Error Amplifier Output for PFC Voltage Feedback Loop. A compensation network (usually a capacitor) is connected between this pin and ground. A large capacitor value results in a narrow bandwidth and improves the power factor. Input AC Current. For normal operation, this input is used to provide current reference for the multiplier. The suggested maximum IAC is 360A. This pin is internally 2 RI 3 4 5 6 7 IEA IPFC IMP ISENSE FBPWM 8 IPWM 9 10 11 12 OPWM GND OPFC VDD 13 SS 14 15 FBPFC VEA 16 IAC (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 5 SG6932 -- PFC / Forward PWM Controller Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltage, are given with respect to GND pin. Stresses beyond those listed under "absolute maximum ratings "may cause permanent damage to the device. Symbol VDD IAC VHIGH VLOW PD TJ TSTG JC TL ESD DC Supply Voltage Input AC Current OPWM, OPFC, IAC Others Parameter Min. Max. 25 2 Unit V mA V V W C C C/W C KV V -0.5 -0.5 -40 -55 DIP SOP 25.0 7.0 0.8 +125 +150 33.64 41.95 +260 4.5 250 Power Dissipation (TA<50C) Operating Junction Temperature Storage Temperature Range Thermal Resistance (Junction-to-Case) Lead Temperature (Wave Soldering, 10 Seconds) Electrostatic Discharge Capability, Human Body Model: JESD22-A114 Electrostatic Discharge Capability, Machine Model: JESD22-A115 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature Min. -40 Typ. Max. +85 Unit C (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 6 SG6932 -- PFC / Forward PWM Controller Electrical Characteristics VDD=15V, TA= 25C unless otherwise noted. Symbol VDD Section VDD-OP IDD ST IDD-OP VTH-ON VDD-min VDD-OVP tVDD-OVP Oscillator VRI fOSC RI RIOPEN RISHORT Parameter Continuously Operating Voltage Start-Up Current Operating Current Start Threshold Voltage Minimum Operating Voltage VDD OVP1 (Turn Off PWM with Delay) Delay Time of VDD OVP1 RI Voltage PWM Frequency RI Range RI Pin Open Protection RI Pin Short Protection RI=24k RI=24k Conditions Min. Typ. Max. 20 Units V A mA V V V s V kHz k k k VDD - 0.16V VDD = 15V; OPFC OPWM open 13 9 23.4 8 1.176 62 12 If RI > RIOPEN, PWM Turned Off If RI > RISHORT, PWM Turned Off 10 6 14 10 24.5 20 10 15 11 25.5 25 1.200 65 200 2 1.224 68 47 VRMS for UVP and ON/OFF VRMS-UVP-1 VRMS-UVP-2 RMS AC Voltage Under-Voltage Threshold to Turn Off PFC (with TUVP Delay) for UVP Mode1 Recovery Level on VRMS for UVP Under-Voltage Protection to Turn Off PFC Delay Time (No Delay for Start-up) 0.75 VRMS+0.17 RI=24k 150 UVP-1 0.80 VRMS+0.19 195 UVP-1 0.85 VRMS+0.21 240 UVP-1 V V tUVP ms PFC Stage Voltage Error Amplifier VREF AV Zo OVPFBPFC OVPFBPFC VFBPFC-H GFBPFC-H VFBPFC-L GFBPFC-L IFBPFC-L IFBPFC-H UVPVFB VOFF-FBPFC Reference Voltage Open-Loop Gain Output Impedance PFC Over-Voltage Protection PFC Feedback Voltage Protection Hysteresis Clamp-High Feedback Voltage Clamp-High Gain Clamp-Low Feedback Voltage Clamp-Low Gain Maximum Source Current Maximum Sink Current PFC Feedback Under-Voltage Protection Voltage Level on FBPFC to Disable OPWM 1.5 70 0.35 2.15 2.75 3.20 60 3.10 2.95 3.00 60 110 3.25 90 3.15 0.5 2.85 6.5 2.0 110 0.40 2.20 0.45 2.25 V 2.90 3.30 120 3.20 3.05 V dB k V mV V mA/V V mA/V mA A V Continued on following page... (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 7 SG6932 -- PFC / Forward PWM Controller Electrical Characteristics (Continued) VDD=15V, TA= 25C unless otherwise noted. Symbol VFBHIGH VRD-FBPFC tUVP_PFC VOFFSET AI BW CMRR VOUT-HIGH VOUT-LOW IMR1, IMR2 IL IH IP Vpk tpkD tBnk Multiplier IAC IMO-max IMO-1 IMO-2 VIMP Parameter Output High Voltage on VEA Conditions Min. 6 2.6 40 Typ. 7 2.7 70 8 60 1.5 Max. 8 2.8 120 Units V V s mV dB MHz dB V Voltage Level on FBPFC to Enable OPWM During Start-up Debounce Time of PFC UVP Input Offset Voltage ((-) > (+)) Open-loop Gain Unit Gain Bandwidth Common-Mode Rejection Ratio Output HIGH Voltage Output LOW Voltage Reference Current Source Maximum Source Current Maximum Sink Current Constant Current Output Peak Current Limit Threshold Voltage Cycle-by-Cycle Limit (Vsense < Vpk) Propagation Delay Leading-Edge Blanking Time Input AC Current Maximum Multiplier Current Output Multiplier Current Output (Low-Line, High-Power) Multiplier Current Output (High-Line, High-Power) Voltage of IMP Open Output Voltage Maximum (Clamp) Output Voltage Low Output Voltage High Rising Time Falling Time Maximum Duty Cycle Multiplier Linear Range RI=24k VRMS=1.05V; IAC=90A; VEA=7.5V; RI=24k VRMS=3V; IAC=264A; VEA=7.5V; RI=24k RI=24k VRMS=1.05V VRMS=3V RI=24k (IMR=20+IRI*0.8) VCM=0~1.5V Current Error Amplifier 70 3.2 0.2 50 3 0.25 90 0.15 0.35 270 0 230 200 65 3.4 230 85 3.9 4.4 280 100 0.20 0.40 350 110 0.25 0.45 200 450 360 70 V A mA mA A V ns ns A A A A V Peak Current Limit PFC Output Driver VZ-PFC VOL-PFC VOH-PFC tR-PFC tF-PFC DCMAX VDD=20V VDD=15V; IO=100mA VDD=13V; IO=100mA VDD=15V; CL=5nF; O/P= 2V to 9V VDD=15V; CL=5nF; O/P= 9V to 2V 8 40 40 93 70 60 120 110 97 16 18 1.5 V V V ns ns % Continued on following page... (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 8 SG6932 -- PFC / Forward PWM Controller Electrical Characteristics (Continued) VDD=15V, TA= 25C unless otherwise noted. Symbol PWM Stage FBPWM AV ZFB FBOPEN-LOOP tOPEN-PWMHiccup Parameter Conditions Min. Typ. Max. Units FB to current Comparator Attenuation Input Impedance PWM Open-Loop Protection Voltage Interval of PWM Open-Loop Protection Reset PWM Open-Loop Protection Delay Time RI=24k RI=24k 2.2 4 4.2 500 80 1.9 2.7 5 4.5 600 95 2.1 3.2 7 4.8 700 120 2.3 V/V k V ms ms V tOPEN-PWM VN Frequency Reduction Threshold on FBPWM Propagation Delay to Output - VLIMIT Loop Leading-Edge Blanking Time Slope Compensation VS=VSLOPE(ton/t) VS : Compensation Voltage Added to Current Sense Output Voltage Maximum (Clamp) Output Voltage Low Output Voltage High Rising Time Falling Time VDD=15V, OPWM Drops to 9V PWM Current Sense tPD-PWM VLIMIT tBnk-PWM VSLOPE Output Driver VZ-PWM VOL-PWM VOH-PWM tR-PWM tF-PWM VDD=20V VDD=15V; IO=100mA VDD=13V; IO=100mA VDD=15V; CL=5nF; O/P=2V to 9V VDD=15V; CL=5nF; O/P=9V to 2V RI=24k RI=24k 8 30 30 60 50 120 110 16 18 1.5 V V V ns ns 60 0.65 270 0.40 0.70 350 0.45 120 0.75 450 0.55 ns V ns V Peak Current Limit Threshold Voltage Maximum Duty Cycle DCSS=6V DCSS=5V Soft Start ISS VDC-MAX-50% VDC-MAX-65% RD Constant Current Output for Soft-Start RI=24k 44 50 56 5 6 470 A V V Maximum Duty Cycle for SS=6V Maximum Duty Cycle for SS=5V 62 46 66 50 % % Voltage of SS for 50% Maximum Duty Cycle Voltage of SS for 65% Maximum Duty Cycle Discharge Resistance (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 9 SG6932 -- PFC / Forward PWM Controller Typical Characteristics 20.0 18.0 16.0 14.0 IDD ST (A) 11.0 10.8 10.6 10.4 VTH-MIN(V) 12.0 10.0 8.0 6.0 4.0 2.0 0.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature () 10.2 10.0 9.8 9.6 9.4 9.2 9.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature () Figure 5. Startup (IDD-ST) vs. Temperature Figure 6. Minimum Operation Voltage (VDD-MIN) vs. Temperature 15.0 14.8 14.4 VTH-ON(V) 14.2 14.0 13.8 13.6 13.4 13.2 13.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Start-up Current (A) 14.6 10.0 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 VDD Voltage (V) Temperature () Figure 7. Start Threshold Voltage (VTH-ON) vs. Temperature Figure 8. Startup Current vs. VDD Voltage 70.0 60.0 50.0 Duty Cycle (%) 25.5 25.3 25.1 VDD-OVP (V) 24.9 24.7 24.5 24.3 24.1 23.9 23.7 23.5 40.0 30.0 20.0 10.0 0.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 FB Voltage (V) Temperature () Figure 9. Duty Cycle vs. FB Voltage Figure 10. VDD OVP Threshold vs. Temperature (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 10 SG6932 -- PFC / Forward PWM Controller Typical Characteristics (Continued) 3.30 3.29 3.28 3.27 OVPPFC (V) 3.25 3.24 3.23 3.22 3.21 3.20 -40 -25 -10 5 20 35 50 65 80 95 110 125 FOSC (KHz) 3.26 68.0 67.5 67.0 66.5 66.0 65.5 65.0 64.5 64.0 63.5 63.0 62.5 62.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature () Temperature () Figure 11. PFC Over-voltage Protection vs. Temperature Figure 12. PWM Frequency (fOSC) vs. Temperature 100.0 90.0 80.0 TR(nS) 100.0 90.0 80.0 TF (nS) 70.0 60.0 50.0 40.0 30.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 70.0 60.0 50.0 40.0 30.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature () Temperature () Figure 13. Rising Time vs. Temperature Figure 14. Falling Time vs. Temperature 3.05 3.04 3.03 3.02 DCMAX (%) 50.0 49.5 49.0 48.5 48.0 47.5 47.0 46.5 46.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 VREF (V) 3.01 3.00 2.99 2.98 2.97 2.96 2.95 Temperature () Temperature () Figure 15. Reference Voltage vs. Temperature Figure 16. Maximum Duty Cycle (SS=5V) vs. Temperature (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 11 SG6932 -- PFC / Forward PWM Controller Typical Characteristics (Continued) 66.0 65.5 65.0 DCMAX (%) 120.0 110.0 100.0 TR-PWM (nS) 64.5 64.0 63.5 63.0 62.5 62.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 90.0 80.0 70.0 60.0 50.0 40.0 30.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature () Temperature () Figure 17. Maximum Duty Cycle (SS=6V) vs. Temperature 4.80 4.75 4.70 4.65 4.60 4.55 4.50 4.45 4.40 4.35 4.30 4.25 4.20 -40 -25 -10 5 20 35 50 65 80 95 110 125 Figure 18. Rising Time vs. Temperature 110.0 100.0 90.0 TF-PWM (nS) FBOPEN-LOOP (V) 80.0 70.0 60.0 50.0 40.0 30.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature () Temperature () Figure 19. PWM Open-Loop Protection Voltage vs. Temperature 120 115 TOPEN-PWM (mS) Figure 20. Fall Time vs. Temperature 55 54 53 52 ISS (uA) -40 -25 -10 5 20 35 50 65 80 95 110 125 110 105 100 95 90 85 80 Temperature () 51 50 49 48 47 46 45 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature () Figure 21. PWM Open-Loop Protection Delay Time vs. Temperature 0.75 0.74 0.73 0.72 VLIMIT (V) Figure 22. Constant Current Output for Soft-start vs. Temperature 0.71 0.70 0.69 0.68 0.67 0.66 0.65 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature () Figure 23. Peak Current Limit Threshold Voltage vs. Temperature (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 12 SG6932 -- PFC / Forward PWM Controller Functional Description The highly integrated SG6932 is designed for power supplies with boost PFC and forward PWM. It requires very few external components to achieve versatile protections and compensation. The proprietary interleave-switching feature synchronizes the PFC and PWM stages and reduces switching noise. At light load, the switching frequency is linearly decreased to reduce power consumption. The PFC function is implemented by average-currentmode control. The proprietary switching charge multiplier-divider provides a high degree of noise immunity for the PFC circuit. This enables the PFC circuit to operate over a much wider region. The proprietary multi-vector output voltage control scheme provides a fast transient response in a low-bandwidth PFC loop; in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop; is broken, the SG6932 shuts off PFC to prevent extrahigh voltage on output. For the forward PWM, the synchronized slope compensation ensures the stability of the current loop under continuous-mode operation. Hiccup operation during output overloading is guaranteed. To prevent the power supply from drawing large current during startup, the start-up for PWM stage is delayed 4ms after the PFC output voltage reaches its set value. SG6932 provides complete protection functions, such as brownout protection and built-in latch for overvoltage and RI open/short. Switching Frequency / Current Sources The switching frequency can be programmed by the resistor RI connected between the RI and GND pins. The relationship is: fPWM = 1560 (kHz ) R I (k ) (1) For example, a 24k resistor RI results in a 65kHz switching frequency. Accordingly, constant current IT flows through RI: IT = 1.2V (mA) RI (k ) (2) IT is used to generate internal current reference. Line Voltage Detection (VRMS) Figure 25 shows a resistive divider with low-pass filtering for line-voltage detection on the VRMS pin. The VRMS voltage is used for the PFC multiplier and brownout protection. For brownout protection, when the VRMS voltage drops below 0.8V, OPFC turns off. 0.47F~4.7F IAC Signal Figure 24 shows the IAC pin connected to input voltage by a resistor and the current, IAC, is the input for PFC multiplier. For the linear range of IAC 0~360A, the range input voltage should be connected to a resistance over 1.2M. Figure 25. Line-Voltage Detection on VRMS Pin Interleave Switching The SG6932 uses interleaved switching to synchronize the PFC and PWM stages. This reduces switching noise and spreads the EMI emissions. Figure 26 shows off-time (tOFF) inserted between the turn-off of the PFC gate drives and the turn-on of the PWM. OPFC OPWM TOFF tOFF Figure 24. Input Voltage Detection Figure 26. Interleaved Switching (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 13 SG6932 -- PFC / Forward PWM Controller PFC Operation The purpose of a boost active power factor corrector (PFC) is to shape the input current of a power supply. The input current waveform and phase follow that of the input voltage. Average-current-mode control is utilized for continuous-current-mode operation for the PFC booster. With the innovative multi-vector control for voltage loop and switching charge multiplier-divider for current reference, excellent input power factor is achieved with good noise immunity and transient response. Figure 27 shows the control loop for the average-current-mode control circuit. The transconductance error amplifier has output impedance RO (>90k) and a capacitor CEA (1F ~ 10F) connected to ground (as shown in Figure 28). This establishes a dominant pole f1 for the voltage loop: f1 = 1 2 x RO x CEA (5) The average total input power can be expressed as: PIN = VIN(rms ) x IIN(rms ) VRMS x IMO I x VEA VRMS x AC VRMS2 VRMS x VIN x VEA R AC VRMS2 VEA (6) From Equation 6, VEA, the output of the voltage error amplifier, actually controls the total input power and the power delivered to the load. Multi-vector Error Amplifier Figure 27. Control Loop of PFC Stage The current source output from the switching charge multiplier-divider can be expressed as: I x VEA ( A) IMO = K x AC VRMS2 (3) IMP, the current output from IMP pin, is the summation of IMO and IMR1. IMR1 and IMR2 are identical, fixed-current sources. R2 and R3 are also identical and are used to pull HIGH the operating point of the IMP and IPFC pins when the voltage across RS goes negative with respect to ground. Through the differential amplification of the signal across RS, better noise immunity is achieved. The output of IEA is compared with an internal sawtooth and the pulsewidth for PFC is determined. Through the average-current-mode control loop, the input current IS is proportional to IMO: IMO x R2 = IS x RS The voltage-loop error amplifier is transconductance, which has high output impedance (> 90k). A capacitor CEA (1F ~ 10F) connected from VEA to ground provides a dominant pole for the voltage loop. Although the PFC stage has a low bandwidth voltage loop for better input power factor, the innovative multi-vector error amplifier provides a fast transient response to clamp the overshoot and undershoot of the PFC output voltage. Figure 28 shows the block diagram of the multi-vector error amplifier. When the variation of the feedback voltage exceeds 5% of the reference voltage, the transconductance error amplifier adjusts its output impedance to increase the loop response. If RA is opened, SG6932 shuts off immediately to prevent extra-high voltage on the output capacitor. SG69XX 3.15V + (4) 2.85V According to Equation 4, the minimum value of R2 and maximum of RS can be determined because IMO should not exceed the specified maximum value. There are different considerations in determining the value of the sense resistor RS. The value of RS should be small enough to reduce power consumption, but large enough to maintain the resolution. A current transformer (CT) may be used to improve the efficiency of high-power converters. To achieve good power factor, the voltage for VRMS and VEA should be kept as DC as possible, according to Equation 3. Good RC filtering for VRMS and narrow bandwidth (lower than the line frequency) for voltage loop are suggested for better input current shaping. RA RB FBPFC 3V + K IACxVEA VRMS 2 VEA CEA Figure 28. Multi-Vector Error Amplifier (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 14 SG6932 -- PFC / Forward PWM Controller Cycle-by-Cycle Current Limiting SG6932 provides cycle-by-cycle current limiting for both PFC and PWM stages. Figure 29 shows the peak current limit for the PFC stage. The PFC gate drive is terminated once the voltage on the ISENSE pin goes below VPK. The VRMS voltage determines the VPK voltage. The relationship between VPK and VRMS is shown in Figure 29. The amplitude of the constant current, IP, is determined by the internal current reference, IT, according to the following equation: IP = 2 x IT = 2 x 1.2(V ) RI Forward PWM and Slope Compensation The PWM stage is designed for forward power converters. Peak-current-mode control is used to optimize system performance. Slope compensation is added to stabilize the current loop. The SG6932 inserts a synchronized, positively sloped ramp at each switching cycle. The positively sloped ramp is represented by the voltage signal Vs-comp. In this example, the voltage of the ramp signal is 0.55V. 0.55V FBPWM (7) + + IPWM Therefore, the peak current of the IS is given by (VRMS<1.05V): (I x RP ) - 0.2(V) IS _ peak = P RS 0.7V (8) SG69XX Figure 31. Slope Compensation Limited Power Control Every time the output of power supply is shorted or overloaded, the FBPWM voltage increases. If the FB voltage is higher than a designed threshold of 4.2V for longer than 95ms, the PWM output is turned off. Gate Drivers Figure 29. Current Limit SG6932 output stages are fast totem-pole gate drivers. The output driver is clamped by an internal 18V Zener diode to protect the power MOSFET. Power-On Sequence and Soft-Start The SG6932 is enabled whenever the line voltage is higher than the brownout threshold. Once the SG6932 is active, the PFC stage is enabled first. The PWM stage is enabled following a 4ms delay time after FBPFC voltage exceeds 2.7V. During start-up of PWM stage, the SS pin charges an external capacitor with a constant current source. The voltage on FBPWM is clamped by SS during start-up. In the event of a protection condition occurring and/or PWM being disabled, the SS pin is quickly discharged. 3V 2.7V FBPFC Protections The SG6932 provides full protection functions to prevent the power supply and the load from being damaged. The protection features include: PFC Feedback Over-Voltage Protection. When the PFC feedback voltage exceeds the over-voltage threshold, SG6932 inhibits the PFC switching signal. This protection prevents the PFC power converter from operating abnormally while the FBPFC pin is open. Second PFC Over-Voltage Protection (OVP_PFC). The PFC stage over-voltage input. The comparator disables the PFC output driver if this input exceeds 3.25V. This pin can be connected to the FBPFC pin or the PFC boost output through a divider network. This pin provides an extra input for PFC over-voltage protection. PFC Feedback Under-Voltage Protection. The SG6932 stops the PFC switching signal whenever the PFC feedback voltage drops below the under-voltage threshold. This protection feature prevents the PFC power converter from experiencing abnormal conditions while the FBPFC pin is shorted to ground. VDD Over-Voltage Protection. The PFC and PWM stages are disabled whenever the VDD voltage exceeds the over-voltage threshold. RI Pin Open / Short Protection. The RI pin is used to set the switching frequency and internal current reference. The PFC and PWM stages of SG6932 are disabled whenever the RI pin is short or open. www.fairchildsemi.com 15 OPFC 4ms OPWM Figure 30. Power-On Sequence (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 SG6932 -- PFC / Forward PWM Controller PCB Layout SG6932 has a single ground pin, which prevents high sink currents in the output being returned separately. Good high-frequency or RF layout practices should be followed. Avoid long PCB traces and component leads. Locate decoupling capacitors near the SG6932. A resistor (5 ~ 20) is recommended, connected in series from the output to the gate of the MOSFET. Isolating the interference between the PFC and PWM stages is also important. Figure 32 shows an example of the PCB layout. The ground trace 1 is connected from the ground pin to the decoupling capacitor, which should be low impedance and as short as possible. The ground trace 2 provides a signal ground and should be connected directly to the decoupling capacitor CDD and/or to the ground pin. The ground trace 3 is independently tied from the decoupling capacitor to the PFC output capacitor CO. The ground in the output capacitor CO is the major ground reference for power switching. To provide a good ground reference and reduce the switching noise of both the PFC and PWM stages, the ground traces 6 and 7 should be located very near and be low impedance. The IPFC pin is connected directly to RS through R3 to improve noise immunity. Do not incorrectly connect to the ground trace 2. The IMP and ISENSE pins should also be connected directly via the resistors R2 and RP to another terminal of RS. Figure 32. PCB Layout (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 16 SG6932 -- PFC / Forward PWM Controller Reference Circuit Figure 33. Reference Circuit (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 17 SG6932 -- PFC / Forward PWM Controller Physical Dimensions A 16 19.68 18.66 9 6.60 6.09 1 8 (0.40) TOP VIEW 0.38 MIN 5.33 MAX 3.42 3.17 3.81 2.92 2.54 0.58 A 0.35 1.78 1.14 17.78 SIDE VIEW NOTES: UNLESS OTHERWISE SPECIFIED A THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BB B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR PROTRUSIONS D) CONFORMS TO ASME Y14.5M-1994 E) DRAWING FILE NAME: N16EREV1 8.13 7.62 0.35 0.20 8.69 15 0 Figure 34. 16-pin Dual In-Line Package (DIP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 18 SG6932 -- PFC / Forward PWM Controller Physical Dimensions (Continued) Figure 35. 16-Pin Small Outline Package (SOIC) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 19 SG6932 -- PFC / Forward PWM Controller (c) 2007 Fairchild Semiconductor Corporation SG6932 * Rev. 1.1.3 www.fairchildsemi.com 20 |
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